Intelligent cell discard schemes have been proposed to allow better throughput in ATM cell switches. ATM cells may either carry individual data or be part of a segmented larger data packet in accordance with AAL5 (ATM Adaptation Layer 5). Individual data cells may be discarded at random when a switch is congested. However, for an AAL5 connection, all ATM cells which comprise a single packet must be delivered through the network to the destination without loss. If a single cell is lost within a packet, the destination will not be able to reconstitute (or reassemble) the packet, and all the other cells received within that packet will be worthless and must be discarded. It will be noted that packets may comprise dozens, or even hundreds of cells.
Intelligent cell discard schemes, often referred to as "Early packet (or Cell) Discard", detect the end of a packet by reading the 3-bit Payload Type (PT) field value of 0X1 (hexadecimal 1) in the ATM cell header, and then setting a flag. When the next user data cell arrives, with a PT value of 0X0 (hexadecimal 0), the level of congestion in the switch is assessed to determine whether there is capacity to accept the entire packet without cell loss. A flag is then set to indicate either acceptance of the whole packet, or that the whole packet is to be discarded. In this way, individual cells within a packet should not be discarded.
Switches become congested when the total input bandwidth exceeds the output bandwidth at a particular switch queuing point. In a typical switch, for example of the type described and claimed in our earlier UK Patent Applications 9507454.8, 9509483.5 and 9509484.3, congestion may occur on the receive side (input to the switch fabric) if the switch fabric is congested and will not allow further cells to be input. It may also occur on the transmit side (output from the switch fabric) where cells arrive faster than they can be transmitted.